Adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications

摘要

Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed.

主权项

1. An apparatus comprising:
first logic, coupled to a first agent, to detect a first bit pattern that indicates a speculative entry of a second agent into a low power consumption state and to cause freezing of one or more control loops; and second logic to detect a second bit pattern that indicates exit from the low power consumption state by the second agent and to cause unfreezing of the one or more control loops, wherein the second logic is to cause unfreezing of all of the one or more control loops in response to detection of the second bit pattern and a determination that that the second agent has not entered the low power consumption state.