| 摘要 |
PROBLEM TO BE SOLVED: To shorten a design period.SOLUTION: A processor 2 is configured to: arrange a dummy pattern 5b in each of first layer circuit blocks 5, 7, 8 included in hierarchical design data 4 on a semiconductor device; set arrangement candidate regions 5c, 7a, 8a as candidates where a dummy pattern 9 may be arranged, in a region between a circuit block border and the dummy pattern 5b in which the dummy pattern 5b is not arranged, in each of the circuit blocks 5, 7, 8; arrange the circuit blocks 5, 7, 8 in an upper layer region 6 on a second layer higher than the first layer; and arrange the dummy pattern 9 in a part of combining the arrangement candidate region 7a in the circuit block 7 and the arrangement candidate region 8a in the circuit block 8 that contact with each other of the arrangement candidate regions 5c, 7a, 8a in the respective circuit blocks 5, 7, 8 arranged in the upper layer region 6.SELECTED DRAWING: Figure 1 |
