REDUCED VOLUME INTERCONNECT FOR THREE-DIMENSIONAL CHIP STACK

摘要

A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.

主权项

1. A method of forming a reduced volume interconnect for a chip stack including a plurality of silicon layers, the method comprising:
forming a plurality of conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy (UBM) pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers in such a manner that at least a given one of the conductive structures between aligned electrical contact locations on corresponding adjacent silicon layers collapses to reduce an interconnect gap therebetween.