| 摘要 |
PROBLEM TO BE SOLVED: To appropriately set dead time and to prevent a through current. SOLUTION: An output buffer 10 includes a high side transistor M1 and a low side transistor M2 serially connected between a power supply terminal 102 and a grounding terminal GND. A delay circuit 12 receives pulse signals S0 whose signal level is switched corresponding to the on and off of the high side transistor M1 and the low side transistor M2. The delay circuit 12 generates a first pulse signal S1 and a second pulse signal S2 having different delays by delaying the pulse signals S0. A NAND circuit 14 supplies signals corresponding to the negative AND of the first pulse signals S1 and the second pulse signal S2 to the gate of the high side transistor M1. An NOR circuit 16 supplies signals corresponding to the negative OR of the first pulse signal S1 and the second pulse signal S2 to the other gate of the low side transistor M2. COPYRIGHT: (C)2008,JPO&INPIT
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