发明名称 FLIP-FLOP CIRCUIT CONTROL METHOD AND METHOD FOR GENERATING CLOCK
摘要 <P>PROBLEM TO BE SOLVED: To reduce the consumption electric power of the flip-flop circuit in scan shift. <P>SOLUTION: At constituting of the scan chains, a part of master latches are mutually connected. Thus, the amount of the circuit is reduced, and the consuming electric power of the scan chain can be reduced, furthermore by reducing the consumption of electric power, the current flowing in the latch circuit can be reduced; and by reducing the current the electromigration (phenomenon which causes short circuiting, increase in resistance, circuit opening, and the like, by the migration of metal ions in the circuit, due to the flow of the electrons to the silicon substrate with the lapse of time) physical deterioration of the semiconductor can be prevented. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009002908(A) 申请公布日期 2009.01.08
申请号 JP20070166554 申请日期 2007.06.25
申请人 FUJITSU LTD 发明人 SATSUKAWA SADAHIKO
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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