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发明名称
Einrichtung und Verfahren zum Entwurf von logischen Schaltungen mit reduziertem Leckstrom
摘要
申请公布号
DE60220471(T2)
申请公布日期
2008.02.07
申请号
DE20026020471T
申请日期
2002.04.02
申请人
KABUSHIKI KAISHA TOSHIBA
发明人
USAMI, KIMIYOSHI;KAWABE, NAOYUKI;KITAHARA, TAKESHI;KANAZAWA, MASAHIRO
分类号
H03K19/003;G06F17/50;H01L21/82;H01L21/8234;H01L27/088;H03K19/00
主分类号
H03K19/003
代理机构
代理人
主权项
地址
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