| 摘要 |
[Problem] To provide a register control method and device that eliminate the need for monitoring gate signals from an operator. [Solution] The timing near the center of a detection pulse 7C1 of a register mark 7C among two register marks 7C and 7D is determined on the basis of the time that has elapsed from the leading edge timing to the trailing edge timing of the detection pulse 7C1, and the timing of a validity period T0 of a new gate signal Vgate_D1 is controlled such that the timing near the center of the validity period T0 coincides with the timing near the center of the detection pulse 7C1. |
