| 摘要 |
Disclosed is a fast Fourier transform device having an eight-parallel multi-path delay commutator (MDC) architecture, capable of reducing hardware complexity. According to one embodiment of the present invention, the fast Fourier transform device having the eight-parallel MDC architecture includes: a first processing module having a plurality of stages, in which each of the stages includes at least one from a plurality of first butterflies, a plurality of delay elements, a plurality of constant multipliers, and a plurality of first commutators; a second processing module having a plurality of stages of which the number of stages is smaller than the number of stages included in the first processing module, in which each of the stages includes a plurality of second butterflies; and a data reconfiguring module arranged between the first processing module and the second processing module, and including a plurality of second commutators for switching an output signal of the first processing module to transmit the output signal to the second processing module as an input signal, and a plurality of complex multipliers connected to the remaining output terminals except one output terminal among output terminals of the respective second commutators. |
