| 摘要 |
PROBLEM TO BE SOLVED: To provide design and test methodology for breaking a linear relation between a defect detecting range or test possibility and a design test or a cost related to production. SOLUTION: The present invention relates to a test assembly for testing a product circuit of a product die, and a product and a test die are prepared on a semiconductor wafer. The product circuit and a test circuit are divided into individual dies to eliminate or minimize the embedded test circuit on the product die 616. This provides a tendency of reducing a size of the product die, of reducing a production cost for the product die, and of maintaining a high-level test range for the product circuit in the product die. Then, the large number of product dies on one or more of wafer(s) can be tested using a test die 618. COPYRIGHT: (C)2005,JPO&NCIPI |
