发明名称 |
Method of forming an integrated multichannel device and single channel device structure |
摘要 |
An integrated circuit is disclosed that includes a single channel device having a first portion of a single shared heterostructure overlying a substrate structure in a single channel device area, and a gate contact that is in contact with the first portion of the single shared heterostructure. The integrated circuit also includes a multichannel device comprising a second portion of the single shared heterostructure overlying the substrate structure in a multichannel device area, a barrier layer overlying the second portion of the single shared heterostructure, and a superlattice structure overlying the barrier layer, the superlattice structure comprising a plurality of heterostructures. An isolation region in the single shared heterostructure electrical isolates the single channel device from the multichannel device. |
申请公布号 |
US9385224(B2) |
申请公布日期 |
2016.07.05 |
申请号 |
US201414458906 |
申请日期 |
2014.08.13 |
申请人 |
Northrop Grumman Systems Corporation |
发明人 |
Renaldo Karen M.;Stewart Eric J.;Howell Robert S.;Henry Howell George;Cramer Harlan Carl;Parke Justin Andrew;King Matthew Russell |
分类号 |
H01L29/76;H01L31/072;H01L31/109;H01L31/0328;H01L31/0336;H01L29/778;H01L21/02;H01L21/76;H01L29/06;H01L21/302;H01L29/66 |
主分类号 |
H01L29/76 |
代理机构 |
Tarolli, Sundheim, Covell & Tummino LLP |
代理人 |
Tarolli, Sundheim, Covell & Tummino LLP |
主权项 |
1. A method of forming an integrated multichannel device and single channel device structure, the method comprising:
depositing a single shared heterostructure over a substrate structure; depositing a barrier layer over the single shared heterorstructure; forming a superlattice structure comprising a plurality of heterostructures over the barrier layer; etching away a portion of superlattice structure over a single channel area to the barrier layer; etching away a portion of the barrier layer over the single channel area to expose a top surface of the single shared heterostructure over the single channel area; forming an isolation region on the single shared heterostructure to isolate the single channel area from a multichannel area to provide a single channel device electrically isolated from a multichannel device; and performing a gate contact fill process to form a first gate contact for the single channel device and a second gate contact for the multichannel device. |
地址 |
Falls Church VA US |