Semiconductor device and method of forming an embedded SOP fan-out package

摘要

A semiconductor device includes a ball grid array (BGA) package including first bumps. A first semiconductor die is mounted to the BGA package between the first bumps. The BGA package and first semiconductor die are mounted to a carrier. A first encapsulant is deposited over the carrier and around the BGA package and first semiconductor die. The carrier is removed to expose the first bumps and first semiconductor die. An interconnect structure is electrically connected to the first bumps and first semiconductor die. The BGA package further includes a substrate and a second semiconductor die mounted, and electrically connected, to the substrate. A second encapsulant is deposited over the second semiconductor die and substrate. The first bumps are formed over the substrate opposite the second semiconductor die. A warpage balance layer is formed over the BGA package.

主权项

1. A method of making a semiconductor device, comprising:
providing a semiconductor package further including,
(a) providing a substrate,(b) disposing a first semiconductor die below a first surface of the substrate,(c) depositing a first encapsulant below the first semiconductor die and completely covering the first surface of the substrate, and(d) disposing a plurality of first bumps directly on a second surface of the substrate opposite the first surface; disposing a second semiconductor die over the second surface of the substrate between the first bumps including a back surface of the second semiconductor die oriented toward the second surface of the substrate; depositing a second encapsulant around the substrate, first semiconductor die, first encapsulant, first bumps, and second semiconductor die, wherein an active surface opposite the back surface of the second semiconductor die and a portion of the first bumps are exposed from the second encapsulant; forming a first insulating layer over the second encapsulant and the active surface of the second semiconductor die; forming a first conductive layer in contact with a contact pad of the second semiconductor die, the exposed portion of the first bumps, and the first insulating layer; and forming an interconnect structure over the first conductive layer, wherein a height of the semiconductor device is less than 1 millimeter (mm).