Shift Register Unit and Driving Method thereof, Shift Register Circuit, and Display Apparatus

摘要

The application relates to a shift register unit and a driving method thereof, a shift register circuit and a display apparatus. The shift register unit may include a gate starting terminal, a first clock terminal, a second clock terminal, a reset terminal, a low level terminal, a gate output terminal, a storage capacitor, a charging module, an output control module and a reset module. In the shift register according to the present application, since the reset operation is under control of the second transistor and the fifth transistor both, an improper reset operation will not occur, even if the signal at the reset terminal is unstable.

主权项

1. A shift register unit, including:
a gate starting terminal; a first clock terminal; a storage capacitor; a charging module, connected with the gate starting terminal, the first clock terminal and the storage capacitor, and adapted to charge the storage capacitor to a high level under control of the gate starting terminal and the first clock terminal; a second clock terminal; a gate output terminal; an output control module, connected with the second clock terminal, the storage capacitor and the gate output terminal, and adapted to output a level signal of the second clock terminal to the gate output terminal when the storage capacitor is at a high level; a reset terminal; a low level terminal; and a reset module, including a second transistor, a fourth transistor and a fifth transistor, wherein a gate of the second transistor is connected to the reset terminal, a source thereof is connected to a first terminal of the storage capacitor, and a drain thereof is connected to a gate of the fifth transistor; a gate of the fourth transistor is connected to the reset terminal, a source thereof is connected to the gate output terminal, and a drain thereof is connected to the low level terminal; a source of the fifth transistor is connected to the first terminal of the storage capacitor, and a drain thereof is connected to the low level terminal; the second transistor and the fifth transistor are used to connect the first terminal of the storage capacitor with the low level terminal under control of the reset terminal, the fourth transistor is used to connect the gate output terminal with the low level terminal under control of the reset terminal.