| 摘要 |
Provided is a storage unit of a static random access memory based on resistance reinforcement, comprising a latch circuit and a bit selection circuit, wherein the latch circuit is composed of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistance capacitance network and a second resistance capacitance network; the bit selection circuit is composed of NMOS transistors N5 and N6; and the latch circuit forms four storage points X1, X1B, X2 and X2B; with respect to the traditional 6T structure storage unit, a resistance capacitance network is added, so that it is guaranteed that single event upset will not occur in a storage unit and it is guaranteed that data is correct at the cost of slight augmentation of areas, without changing an original operation access and increasing obvious complexity. |
