Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals

摘要

A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

主权项

1. A method comprising:
receiving a control signal to operate a memory device in power down state associated with an asynchronous mode of operation for on-die termination (ODT) circuitry; determining a sufficiency of clock signals for a synchronous mode of operation when a clock pulse occurs in a first input clock signal based on a rising edge of an external clock signal or a second input clock signal based on a failing edge of the external clock signal during half of a clock period of the external clock signal; determining an insufficiency of clock signals for a synchronous mode of operation when no clock pulses occur for both the first input clock signal and the second input clock signal during one clock period of the external clock signal; if the determining indicates sufficiency of clock signals, operating the memory device in the power down state using the synchronous mode of operation; and if the determining indicates insufficiency of clock signals, operating the memory device in the power down state using the asynchronous mode of operation.