Method for fabricating FinFET with separated double gates on bulk silicon

摘要

Disclosed herein is a method for fabricating a FinFET with separated double gates on a bulk silicon, comprising: forming a pattern for a source, a drain and a thin bar connecting the source and the drain; forming an oxidation isolation layer; forming a gate structure and a source/drain structure; and forming a metal contact and a metal interconnection. By means of the method herein, it is very easy to fabricate the FinFET with separated double gates on the bulk silicon wafer, and the overall process flow is completely compatible with the conventional silicon-based very large scale integrated circuit manufacturing technology. Thus, the method herein is simple, convenient and has a short process period, greatly economizing the cost of the silicon wafer. In addition, by employing the FinFET with separated double gates fabricated by the method according to the invention, the short channel effect can be effectively suppressed. Further, the power consumption of the device can be further reduced through the special multi-threshold characteristic of the device with separated double gates.

主权项

1. A method for fabricating a FinFET with separated double gates on a bulk silicon, comprising:
a) forming a pattern for a source, a drain, and a thin bar connecting the source and the drain i. depositing a silicon oxide layer and a silicon nitride layer on a silicon substrate as a hard mask; ii. forming the pattern for a source, a drain and the thin bar connecting the source and the drain in the hard mask through performing an electron beam photolithography process one time and performing an etching process on the silicon nitride layer and the silicon oxide layer; iii. removing an electron beam resist; iv. performing an etching process on the silicon substrate, so as to transfer the pattern on the hard mask onto the silicon substrate; b) forming an oxidation isolation layer i. depositing a further silicon nitride layer; ii. etching the further silicon nitride layer by using an anisotropic dry etching process, so as to form a silicon nitride sidewall on both sides of a Fin bar; iii. etching the silicon substrate exposed on both sides with respect to the Fin bar by using anisotropic dry etching process; iv. forming the oxidation isolation layer on a surface of the substrate which is positioned under the Fin bar and at both sides of the Fin bar by wet oxidizing the surface of the silicon substrate which has been etched by using anisotropic dry etching process; c) forming a gate structure and a source/drain structure i. removing the silicon nitride sidewall and the silicon nitride layer of the hard mask by using a wet etching process; ii. growing a gate oxide layer by using a thermal oxidation process; iii. depositing a polysilicon layer as a gate material; iv. performing a chemical mechanical polishing (CMP) process to planarize the polysilicon layer, the process stopping at a surface of the silicon oxide layer of the hard mask on top of the Fin bar; v. forming polysilicon gate lines by performing an electron beam photolithography process and etching the polysilicon gate material, so that the gate lines on both sides with respect to the Fin bar are not coupled together and are separated from each other; vi. forming silicon oxide sidewalls by using an ion enhanced chemical vapor deposition process and an etch-back process; vii. performing an ion implantation process and a high temperature annealing process so as to form the source/drain structure, wherein: in step b), a connection between the Fin bar and the substrate is completely or partially isolated by the grown oxidation isolation layer.