Semiconductor device comprising an ESD protection device, an ESD protection circuitry, an integrated circuit and a method of manufacturing a semiconductor device

摘要

A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage.

主权项

1. A semiconductor device comprising an ESD protection device for protecting an integrated circuit on the semiconductor device against ESD event received by the integrated circuit, the ESD protection device comprising:
an N-well region arranged in a semiconductor substrate of the semiconductor device and having a surface at a first side of the substrate; a first P+ doped region that abuts the N-well region for forming a collector of a parasitic transistor; a second P+ doped region that abuts the N-well region for forming an emitter of the parasitic transistor, the second P+ doped region being separated from the first P+ doped region by a first portion of the N-well region; a N+ doped region that abuts the N-well region for providing an electrical contact with the N-well region, the N+ doped region being arranged at a larger distance from the first P+ doped region than from the second P+ doped region, the N+ doped region being separated from the second P+ doped region by a second portion of the N-well region; and an electrical connection between the second P+ doped region and the N+ doped region, the electrical connection being arranged in one or more layers which are arranged at the first side of the substrate, wherein no gate is present in a layers manufactured at the first side of the substrate above the first portion of the N-well region, the first side of the semiconductor substrate is unsilicided at the first portion of the N-well region, a P+ doping of the first P+ doped region and the N-well doping are configured to obtain a predefined trigger voltage for triggering the operation of the ESD protection device.