发明名称 |
Electrostatic discharge protection system |
摘要 |
An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit. |
申请公布号 |
US9478529(B2) |
申请公布日期 |
2016.10.25 |
申请号 |
US201414289083 |
申请日期 |
2014.05.28 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
Miller James W.;Etherton Melanie;Gerdemann Alex P.;Moosa Mohamed S.;Phillippe Jonathan M.;Ruth Robert S. |
分类号 |
H02H3/22;H01L27/02;H05K9/00;H02H9/04;H02H3/20;H01L23/00 |
主分类号 |
H02H3/22 |
代理机构 |
|
代理人 |
|
主权项 |
1. An integrated circuit, comprising:
a first power bus; a second power bus; a core region; a plurality of I/O cells around the core region, each I/O cell including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portion of the first power bus and the portion of the second power bus, wherein:
a first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit,a second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge, wherein the first set is between the core region and the second set, andfor each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set; an ESD clamp coupled between the first and second power buses; and a trigger circuit coupled to the ESD clamp. |
地址 |
Austin TX US |