发明名称 RC LATTICE DELAY
摘要 An integrated constant time delay circuit utilized in continuous-time (CT) analog-to-digital converters (ADCs) can be implemented with an RC lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments. A Resistor-Capacitor “RC” lattice structure can be an alternative to a constant-resistance Inductor-Capacitor “LC” lattice implementation. ADC architectures benefit from the RC implementation, due to its ease of impedance scaling and smaller area.
申请公布号 US2016373101(A1) 申请公布日期 2016.12.22
申请号 US201615182430 申请日期 2016.06.14
申请人 ANALOG DEVICES GLOBAL 发明人 Dong Yunzhi;KOZLOV VICTOR;YANG WENHUA W.;CALDWELL TREVOR CLIFFORD;SHIBATA HAJIME
分类号 H03K5/14;H03M3/00;H03H7/30;H03M1/00 主分类号 H03K5/14
代理机构 代理人
主权项 1. A continuous time delay line for a residual producing circuit, the continuous time delay line comprising: a resistor-capacitor (RC) lattice for delaying a differential analog input pair, the RC lattice structure having first and second resistive components and first and second capacitive components, the first and second resistive components being cross coupled with respect to the first and second capacitive components; wherein the delayed differential analog input pair and a filtered version of the differential analog input pair are used to generate a residual signal, and parameters of the RC lattice correspond to a phase component of a circuit path producing the filtered version of the differential analog input pair.
地址 Hamilton BM