发明名称 |
DRIFT DETECTION IN TIMING SIGNAL FORWARDED FROM MEMORY CONTROLLER TO MEMORY DEVICE |
摘要 |
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift. |
申请公布号 |
US2016161977(A1) |
申请公布日期 |
2016.06.09 |
申请号 |
US201514961077 |
申请日期 |
2015.12.07 |
申请人 |
Rambus Inc. |
发明人 |
Kim Jun;Chau Pak Shing;Richardson Wayne S. |
分类号 |
G06F1/08;G06F1/10 |
主分类号 |
G06F1/08 |
代理机构 |
|
代理人 |
|
主权项 |
1. A memory controller comprising:
a timing signal generation circuit to generate, for transmission to a memory device:
a first timing signal having a first frequency, the first timing signal to be used, by the memory device, for a data transfer operation; anda second timing signal having a second frequency, the second frequency being lower than the first frequency; a circuit to receive from the memory device information indicative of phase delay occurring on the second timing signal associated with timing drift in the memory device; and a phase adjusting circuit to adjust a phase of the first timing signal based on the received information indicative of phase delay occurring on the second timing signal. |
地址 |
Sunnyvale CA US |