发明名称 FIRST-ETCHED AND LATER-PACKAGED THREE-DIMENSIONAL SYSTEM-IN-PACKAGE NORMAL CHIP STACK PACKAGE STRUCTURE AND PROCESSING METHOD THEREOF
摘要 A first-etched and later-packaged three-dimensional system-in-package normal chip stack package structure and a processing method for manufacturing the same are provided. The structure includes: a die pad (1); a lead (2); a chip (4) provided on a top surface of the die pad (1) by a conductive or non-conductive adhesive material (3); a metal wire (5) via which a top surface of the chip (4) is connected to a top surface of the lead (2); a conductive pillar (6) provided on the surface of the lead (2); and a molding material (7).
申请公布号 US2016372450(A1) 申请公布日期 2016.12.22
申请号 US201414901483 申请日期 2014.01.08
申请人 JIANGSU CHANGJANG ELECTRONICS, TECHNOLOGY CO., LTD 发明人 Liang Chih-Chung;Wang Yaqin;Zhang Chunyan;Lin Yu-Bin;Zhang Youhai
分类号 H01L25/00;H01L23/31;H01L21/48;H01L21/56;H01L25/065;H01L23/495 主分类号 H01L25/00
代理机构 代理人
主权项 1. A processing method for manufacturing a first-etched and later-packaged three-dimensional system-in-package normal chip stack package, comprising: step 1, providing a metal substrate; step 2, pre-plating a surface of the metal substrate with a micro copper layer; step 3, applying a photoresist film, wherein a top surface and a bottom surface of the metal substrate which have been pre-plated with the micro copper layer are applied with the photoresist film which can be exposed and developed; step 4, removing a part of the photoresist film on the bottom surface of the metal substrate, wherein the bottom surface of the metal substrate, which has been applied with the photoresist film in step 3, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the bottom surface of the metal substrate to be plated later; step 5, plating with a metal wiring layer, wherein the region of the bottom surface of the metal substrate from which the part of the photoresist film has been removed in step 4 is plated with the metal wiring layer; step 6, applying a photoresist film, wherein the bottom surface of the metal substrate in step 5 is applied with the photoresist film which can be exposed and developed; step 7, removing a part of the photoresist film on the bottom surface of the metal substrate, wherein the bottom surface of the metal substrate, which has been applied with the photoresist film in step 6, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the bottom surface of the metal substrate to be plated later; step 8, plating with a high conductivity metal wiring layer, wherein the region of the bottom surface of the metal substrate from which the part of the photoresist film has been removed in step 7 is plated with the high conductivity metal wiring layer, so that a die pad and a lead are formed; step 9, removing the photoresist film, wherein the photoresist film on the surface of the metal substrate is removed; step 10, molding with epoxy resin, wherein the molding with the epoxy resin for protecting is performed on a surface of the metal wiring layer provided on the bottom surface of the metal substrate; step 11, grinding a surface of the epoxy resin, wherein the surface of the epoxy resin is ground after the molding with the epoxy resin has been performed; step 12, applying a photoresist film, wherein the top surface and the bottom surface of the metal substrate are applied with the photoresist film which can be exposed and developed after the surface of the epoxy resin has been ground in step 11; step 13, removing a part of the photoresist film on the top surface of the metal substrate, wherein the top surface of the metal substrate, which has been applied with the photoresist film in step 12, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be etched later; step 14, chemical etching; wherein the chemical etching is performed in the region of the top surface of the metal substrate in which exposing and developing have been performed in step 13; step 15, applying a photoresist film, wherein the top surface and the bottom surface of the metal substrate are applied with the photoresist film which can be exposed and developed after the chemical etching has been performed in step 14; step 16, removing a part of the photoresist film on the top surface of the metal substrate, wherein the top surface of the metal substrate, which has been applied with the photoresist film in step 15, is exposed and developed with a pattern using an exposure and development equipment, and the part of the photoresist film in the pattern is removed, so as to expose a region of the top surface of the metal substrate to be plated later; step 17, plating with a metal pillar, wherein the region of the top surface of the metal substrate from which the part of the photoresist film has been removed in step 16 is plated with the metal pillar; step 18, removing the photoresist film, wherein the photoresist film on the surface of the metal substrate is removed; step 19, coating with an adhesive material; wherein a top surface of the die pad is coated with a conductive or non-conductive adhesive material after the photoresist film on the surface of the metal substrate has been removed in step 18; step 20, bonding dies, wherein a chip bonded in the conductive or non-conductive adhesive material in step 19; step 21, bonding a metal wire, wherein the metal wire is bonded between a top surface of the chip and a top surface of the lead; step 22, encapsulating, wherein the molding with a molding material is performed on the top surface of the metal substrate in step 21; step 23, grinding a surface of an epoxy resin, wherein the surface of the epoxy resin is ground after the molding with the epoxy resin has been performed in step 22; step 24, plating with an anti-oxidizing metal layer or coating with an organic solderability preservative, wherein an exposed surface of the metal substrate is plated with the anti-oxidizing metal layer or is coated with the organic solderability preservative after the surface of the epoxy resin has been ground in step 23; step 25, stacking with a package, wherein a top of the metal pillar or a bottom surface of the lead is stacked with the package after the plating with the anti-oxidizing metal layer or the coating with the organic solderability preservative has been performed in step 24; step 26, package sawing to form a finished product, wherein a semi-finished product is package sawed after the stacking with the package has been performed in step 25 to form a first-etched and later-packaged three-dimensional system-in-package normal chip stack package structure.
地址 Jiangyin, Jiangsu CN