发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME |
摘要 |
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including a plurality of electrode layers separately stacked; a first upper layer gate provided on the stacked body; an interlayer insulating layer provided on the first upper layer gate; an insulating part continuously provided from the first upper layer gate to the substrate and extending in a first direction parallel to a major surface of the substrate; a second upper layer gate; a semiconductor part; a charge storage film; and a semiconductor layer provided from an upper end of the semiconductor part to a portion of the semiconductor part reaching the second upper layer gate. The second upper layer gate is provided on the interlayer insulating layer and the insulating part, and extends on a first surface parallel to the major surface. |
申请公布号 |
US2016225783(A1) |
申请公布日期 |
2016.08.04 |
申请号 |
US201514734379 |
申请日期 |
2015.06.09 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
ISHIBASHI Shota |
分类号 |
H01L27/115;H01L29/66;H01L29/792;H01L29/423 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor memory device comprising:
a substrate; a stacked body provided on the substrate and including a plurality of electrode layers separately stacked; a first upper layer gate provided on the stacked body; an interlayer insulating layer provided on the first upper layer gate; an insulating part continuously provided from the first upper layer gate to the substrate and extending in a first direction parallel to a major surface of the substrate; a second upper layer gate provided on the interlayer insulating layer and the insulating part, and extending on a first surface parallel to the major surface; a semiconductor part extending from the second upper layer gate to the substrate; a charge storage film provided between the semiconductor part and the plurality of electrode layers; and a semiconductor layer provided from an upper end of the semiconductor part to a portion of the semiconductor part reaching the second upper layer gate. |
地址 |
Minato-ku JP |