INTEGRATED CIRCUIT CHIP RELIABILITY USING RELIABILITY-OPTIMIZED FAILURE MECHANISM TARGETING

摘要

Disclosed are methods for improving integrated circuit (IC) chip reliability. IC chips are manufactured and sorted into groups corresponding to process windows within a process distribution for the design. Group fail rates are set for each group based on failure mechanism fail rates, which are set for multiple failure mechanisms. An overall fail rate is determined for the full process distribution based on the group fail rates. First contribution amounts of the groups to the overall fail rate and second contribution amounts of the failure mechanisms to the group fail rate of each group are determined. Based on an analysis of the contribution amounts, at least one specific failure mechanism is selected and targeted for improvement (i.e., changes directed to the specific failure mechanism(s) are proposed and implemented). Optionally, proposed change(s) are only implemented if they will be sufficient to meet a reliability requirement and/or will not be cost-prohibitive.

主权项

1. A method comprising:
sorting integrated circuit chips manufactured according to a design into groups, said groups corresponding to different process windows within a process distribution for said design; setting group fail rates for said groups, each group fail rate for each group being based on failure mechanism fail rates set for multiple failure mechanisms; determining an overall fail rate based on said group fail rates; and, improving integrated circuit chip reliability using reliability-optimized failure mechanism targeting, said improving comprising:
determining first contribution amounts of said groups to said overall fail rate;determining, for each group fail rate of each group, second contribution amounts of said failure mechanisms to said group fail rate;based on an analysis of said first contribution amounts and said second contribution amounts, selecting at least one specific failure mechanism; andimplementing at least one change to at least one process performed during manufacturing of new integrated circuit chips according to said design, said at least one change being directed toward improving said specific failure mechanism.