Memory read circuit with precharging limitation device

摘要

Disclosed is a memory read circuit with a device to limit the precharging of the bit lines. The circuit includes a portion forming a current mirror and providing furthermore for a controlled precharging of the bit line and of the reference line in limiting the precharging potential to a borderline value referenced with respect to the ground. The circuit may be applied to non-volatile (EEPROM, Flash EPROM) memories, and especially memories supplied with low voltages.