发明名称 |
Wafer burn-in test circuit for a semiconductor memory device |
摘要 |
A semiconductor memory device has independently controllable word lines, thereby allowing various background data patterns to be freely written to the memory cells to perform various wafer burn-in tests. This allows the leakage between adjacent memory cells to be efficiently tested by independently controllable word line activation signals, as well as the reliability of bit lines. A wafer burn-in test circuit for performing this improved burn-in test improves the reliability of the device by performing a level transition on the signals that drive the sub word line drivers, thereby eliminating the need to apply a high voltage to one transistor in the sub word line driver.
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申请公布号 |
US5986917(A) |
申请公布日期 |
1999.11.16 |
申请号 |
US19970996806 |
申请日期 |
1997.12.23 |
申请人 |
SAMSUNG ELECTRONICS, CP. LTD. |
发明人 |
LEE, YUN-SANG |
分类号 |
G01R31/26;G11C8/14;H01L21/66;(IPC1-7):G11C17/00 |
主分类号 |
G01R31/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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