| 摘要 |
A field effect transistor configured in a convex type Fin structure, in which diffusion layer 104 serving as source and drain regions is formed in a semiconductor layer that is sandwiched by STI regions 105 and projected upward of the isolation region, and which has a gate electrode overlapping a channel region between the source and drain regions, the field effect transistor including: side walls 110b on the sides of the diffusion layer serving as the source and drain regions; selective epitaxial growth silicon layer 111 on the upper surface of the diffusion layer sandwiched by the side walls; and contact plug 115 connected to the selective epitaxial growth silicon layer. |
