Subthreshold Standard Cell Library

摘要

A subthreshold standard cell library addresses the energy efficiency of electronic systems, thereby significantly reducing power consumption. Recent energy performance requirements are causing the next-generation system manufacturers to explore approaches to lower power consumption. Subthreshold operation has been examined and implemented in designing ultra-low power standard cell designs that operate beyond the normal modes of operation, with the potential for large energy savings. Operation of CMOS (Complementary Metal Oxide Semiconductor) transistors in the subthreshold regime, where the supply voltage used in operation is orders of magnitude below the normal operating voltage of typical transistors, has proven to be very beneficial for energy constrained systems as it enables minimum energy consumption in Application Specific Integrated Circuits (ASICs).

主权项

1. A standard cell logic library for synthesizing an application specific integrated circuit (ASIC) using a TSMC 0.25 μm process, said library comprising:
a plurality of logic gates for synthesizing application specific integrated component circuits, each of said logic gates having a rise and fall delay, and a propagation delay and operating in the subthreshold voltage region; said logic gates components each including different combinations and quantities of n-type and p-type metal oxide semiconductor field effect transistors (nMOS and pMOS) and further having a constant channel length and a nMOS to pMOS ratio R, said ratio R being chosen so that the rise and fall delay and the propagation delay of each said logic gate of said ASIC is substantially equal; an operating Vdd component including positive supply voltages in the subthreshold voltage region for the respective integrated circuits said ASIC; a synthesis library input component including timing, temperature and physical characteristics of the respective integrated circuits for said ASIC; and a physical library component including symbol, schematic and mask layouts for the respective circuits said ASIC.