| 摘要 |
To provide a SiC power MISFET having a low on-resistance and a high withstand voltage. In order to solve the problem, in a SiC power MISFET of the present invention, each of p-type body regions is configured from: a first region having a first depth; and a second region that is formed in contact with the first region on the outer side of the first region in a planar view, said second region having a second depth that is smaller than the first depth. A JFET region is formed deeper than the second depth between the p-type body regions that are adjacent to each other, and the second region of each of the p-type body regions is surrounded by the JFET region, thereby dispersing an electric field applied to a pn junction portion between each of the p-type body regions and the JFET region to a plurality of corner portions. Consequently, since the electric field applied to the pn junction portion is dispersed, reduction of a withstand voltage can be eliminated, even if the JFET region is formed for the purpose of obtaining a low on-resistance. |
