发明名称 |
CIRCUITO DECODIFICATORE DI RIGA PER UN DISPOSITIVO DI MEMORIA NON VOLATILE A CAMBIAMENTO DI FASE |
摘要 |
A row decoder circuit for a phase change non-volatile memory device may include memory cells arranged in a wordlines. The device may be configured to receive a first supply voltage and a second supply voltage higher than the first supply voltage. The row decoder may include a global predecoding stage configured to receive address signals and generate high-voltage decoded address signals in a range of the second supply voltage and a biasing signal with a value based upon an operation. The row decoder may include a row decoder stage coupled to the global predecoding stage. The row decoder stage may include a selection driving unit configured to generate block-address signals based upon the high-voltage decoded address signals and a row-driving unit configured to generate a row-driving signal for biasing the wordlines based upon the block-address signals and the biasing signal. |
申请公布号 |
ITTO20120412(A1) |
申请公布日期 |
2013.11.09 |
申请号 |
IT2012TO00412 |
申请日期 |
2012.05.08 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
CASTAGNA GIUSEPPE;DE SANDRE GUIDO;PERRONI MAURIZIO FRANCESCO;POLIZZI SALVATORE |
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