发明名称 |
DIGITAL PHASE LOCKED LOOP |
摘要 |
PROBLEM TO BE SOLVED: To provide an enhanced system that employs a digital phase locked loop. SOLUTION: The system has a digital phase locked loop(PLL) consisting of a full digital circuit configuration and a standard cell structure. The digital PLL has a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including digital chains, a non-glitch MUX and a phase accumulator. The digital phase detector is electrically coupled with the digital frequency synthesizer and supplies digital code information denoting a phase error between the edge of an input reference signal and the edge of a synthesized signal by comparing the edge of the input reference signal with the edge of the synthesized signal. |
申请公布号 |
JP2001326830(A) |
申请公布日期 |
2001.11.22 |
申请号 |
JP20010085624 |
申请日期 |
2001.03.23 |
申请人 |
STMICROELECTRONICS INC |
发明人 |
ELLIOT WILLIAM D;NEUGEBAUER CHARLES F |
分类号 |
H04N5/12;G09G3/20;G09G5/00;H03K5/00;H03K5/1252;H03K5/13;H03L7/081;H03L7/089;H03L7/091 |
主分类号 |
H04N5/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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