发明名称 |
DECODING TECHNIQUES FOR READ-ONLY MEMORY |
摘要 |
A memory circuit includes a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of column sense logic units are also provided, corresponding to the bit line structures. Each of the column sense logic units includes a first logic gate and a second logic gate. The first logic gate has a first input connected with a first one of the bit lines and a second input connected with a second one of the bit lines. The second logic gate has a first input interconnected with a third one of the bit lines, and a second input interconnected with the second one of the bit lines.
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申请公布号 |
US2007201281(A1) |
申请公布日期 |
2007.08.30 |
申请号 |
US20060363366 |
申请日期 |
2006.02.27 |
申请人 |
DUDECK DENNIS E;EVANS DONALD A;PHAM HAI Q;WERNER WAYNE E;WOZNIAK RONALD J |
发明人 |
DUDECK DENNIS E.;EVANS DONALD A.;PHAM HAI Q.;WERNER WAYNE E.;WOZNIAK RONALD J. |
分类号 |
G11C7/00;G11C7/10;G11C8/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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