SCALING MULTI-CORE NEUROSYNAPTIC NETWORKS ACROSS CHIP BOUNDARIES

摘要

Embodiments of the invention provide a system for scaling multi-core neurosynaptic networks. The system comprises multiple network circuits. Each network circuit comprises a plurality of neurosynaptic core circuits. Each core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of electronic synapse devices. An interconnect fabric couples the network circuits. Each network circuit has at least one network interface. Each network interface for each network circuit enables data exchange between the network circuit and another network circuit by tagging each data packet from the network circuit with corresponding routing information.

主权项

1. A system for scaling multi-core neurosynaptic networks, comprising:
multiple neurosynaptic network circuits, wherein each network circuit comprises a plurality of neurosynaptic core circuits; an interconnect fabric coupling said multiple network circuits; and for each network circuit, at least one corresponding network interface, wherein each network interface for each network circuit enables data exchange between said network circuit and another network circuit of said multiple network circuits by tagging each data packet from said network circuit with corresponding routing information indicating a number of core circuits of said another network circuit that said data packet traverses at least one of horizontally and vertically to reach a target core circuit of said another network circuit; wherein each core circuit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices for interconnecting said multiple neurons with said multiple axons.