| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device for simultaneously covering high processing rate and high integration density. SOLUTION: A standard cell 51a includes CMOS inverters NT1 and PT1. The power supply wire is electrically connected to the CMOS inverters NT1, PT1 and also includes lower layer wires 32a, 32b and upper layer wires 34c, 34d. The lower layer wires 32a, 32b are extended up to the area on the boundary of the neighboring standard cells 51a along the boundary. The upper layer wires 34c, 34d are located at the internal side of the standard cell 51a more than the lower layer wires 32a, 32b in the plan view. The CMOS inverters NT1, PT1 are electrically connected to the lower layer wires 32a, 32b via the upper layer wires 34c, 34d. COPYRIGHT: (C)2009,JPO&INPIT |
