FUNCTIONAL STRUCTURE OF CONDITIONALLY i POSITION OF PARALLEL ADDER FOR TERNARY NUMBER SYSTEM f(+1,0,-1) IN ITS POSITION-SIGN FORMAT f(+/-)

摘要

FIELD: information technologies. ^ SUBSTANCE: invention may be used for building arithmetic units and executing arithmetic operations of summing up and subtracting in position-sign codes. Each adder position is made in the form of two structurally equivalent channels - positive and conditionally negative channels for summing up summands. In one of the implementation versions, each channel includes four OR gates, three OR-NOT gates, six AND gates, AND-NOT gate. ^ EFFECT: device speedup. ^ 2 cl, 9 dwg, 4 ex