发明名称 |
SHARED CONTROL OF A PHASE LOCKED LOOP (PLL) FOR A MULTI-PORT PHYSICAL LAYER (PHY) |
摘要 |
Methods and systems for shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY) are disclosed. In one aspect, an arbitration logic circuit is coupled to ports of a multi-port PHY sharing a phase locked loop (PLL). Upon receiving an indication that the shared PLL is to be reset, the arbitration logic circuit commands the ports sharing the PLL to enter a state in which any reset of the shared PLL would have minimal or no effect in their operations. In this manner, an integrated circuit (IC) including a multi-port PHY may be configured with only one PLL and associated clock generating logic to provide a clock signal for some or all of its ports, thus reducing its semiconductor area and power consumption. Furthermore, the ports of the multi-port PHY may operate independently from each other obviating any configuration and/or interoperability problems associated with having a shared PLL. |
申请公布号 |
WO2016164120(A1) |
申请公布日期 |
2016.10.13 |
申请号 |
WO2016US20352 |
申请日期 |
2016.03.02 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
WINEMILLER, Chad, Everett;BARASH, Dror;DEANS, Russell, Coleman;VILAS, Mark, Wesley |
分类号 |
G06F1/32 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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