| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory apparatus in which relieving efficiency of defective memory cells can be improved. <P>SOLUTION: The apparatus is provided with a plurality of memory cell array (0) to (j), bit lines BL, a column gate 20 selecting a bit line, and an error correcting circuit 16 performing error correction of read out data, the memory cell array includes a first element separation region STI formed periodically and repeatedly in a semiconductor substrate 40 and the memory cells MC formed on an element region AA between adjacent element separation regions STI and the memory cell array is provided with a plurality of first region AAG arranged along the direction of a word line and a second region SA1 including a second element separation region STI which is provided being adjacent to the first region AAG and of which the width is larger than the first element separation region STI, an address of the bit line being adjacent to the second region SA1 is different between the memory cell arrays in the first region AAG. <P>COPYRIGHT: (C)2007,JPO&INPIT |
