发明名称 |
Digital Phase Locked Loop with Integer Channel Mitigation |
摘要 |
An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.
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申请公布号 |
US2008317188(A1) |
申请公布日期 |
2008.12.25 |
申请号 |
US20080024881 |
申请日期 |
2008.02.01 |
申请人 |
STASZEWSKI ROBERT BOGDAN;VEMULAPALLI SUDHEER K;WALLBERG JOHN L;WAHEED KHURRAM |
发明人 |
STASZEWSKI ROBERT BOGDAN;VEMULAPALLI SUDHEER K.;WALLBERG JOHN L.;WAHEED KHURRAM |
分类号 |
H04L7/00 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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