BUCKET BRIGADE ADDRESS DECODING ARCHITECTURE FOR CLASSICAL AND QUANTUM RANDOM ACCESS MEMORIES

摘要

In an address signal decoder for a RAM memory, address signals are decoded in a "bucket brigade" address decoding architecture in which the address signals or bits are sequentially sent along the same address decoding path. The inventive architecture comprises a set of node switches linked into a binary tree. The address signals enter at the root node of the binary tree. As each address signal reaches a node switch at the end the path, it sets the path direction for that switch node so that subsequent address signals that follow the path will use that path direction. The decoder can be used with classical or quantum RAM memories.