| 摘要 |
A discrete-time analog circuit comprises: a voltage-current conversion circuit that converts an input voltage signal into a current signal and outputs the current signal; and a charge inverting circuit that is connected to an output terminal of the voltage-current conversion circuit to perform charge sharing. The charge inverting circuit includes 2M capacitors (M is an integer greater than or equal to 1) that are provided parallel to each other. In accordance with a predetermined sampling interval, one of the 2M capacitors repeats: (1) sharing input charge that is input by the current signal, (2) holding at least part of the input charge, (3) inverting a polarity of the held charge and connecting to the output terminal to share the held charge, and (4) holding remaining charge. At time period when one of the 2M capacitors is connected to the output terminal, the other capacitor(s) of the 2M capacitors is not connected to either of an input terminal and the output terminal. |
| 主权项 |
1. A discrete-time analog circuit, comprising:
a voltage-current conversion circuit including a first terminal and a second terminal, which converts a voltage signal that is input to the first terminal into a current signal, and outputs the current signal from the second terminal; and a charge inverting circuit including a third terminal connected to the second terminal, a fourth terminal, and 2M capacitors (M is an integer greater than or equal to 1) that are provided in parallel between the third terminal and the fourth terminal, wherein, in accordance with a predetermined sampling interval, each of the 2M capacitors repeats: (1) sharing input charge that is at least part of input by the current signal, (2) holding at least part of the input charge, (3) inverting a polarity of the held charge and connecting to the third terminal to share the held charge having the inverted polarity, and (4) holding remaining charge, and wherein at a time period when one of the 2M capacitors is connected to the third terminal, the other capacitor(s) of the 2M capacitors is not connected to the third terminal. |
