MODELING THE PERFORMANCE OF A FIELD EFFECT TRANSISTOR HAVING A DYNAMICALLY DEPLETED CHANNEL REGION

摘要

Disclosed are a system, a method and a computer program product for accurately modeling the performance of a body-contacted, asymmetric double gate, dynamically depleted (DD), semiconductor-on-insulator (SOI) field effect transistor (FET). This modeling can be performed, using iterative processing, to determine the conditions (e.g., back gate bias voltage, front gate bias voltage, body resistance and body charge) under which the FET channel region transitions from being in a partially depleted (PD) state such that the FET functions as a PD SOI FET to being in a fully depleted (FD) state such that the FET functions as a FD SOI FET. Once these conditions are known (i.e., once the model is generated), the DD SOI FET can be incorporated into top-level integrated circuit designs with specifications that either meet the conditions or do not meet the conditions, depending upon the desired function of the DD SOI FET within the integrated circuit.

主权项

1. A system comprising:
a memory storing a design for a dynamically depleted field effect transistor, said dynamically depleted field effect transistor comprising:
a semiconductor layer having a back surface and a front surface opposite said back surface, said semiconductor layer comprising a source region, a drain region, a body region and a channel region within said body region and positioned laterally between said source region and said drain region;a back gate adjacent to said back surface at said channel region; and,a front gate adjacent to said front surface at said channel region and opposite said back gate; and, at least one processor accessing, from said memory, said design and, based on said design, modeling performance of said dynamically depleted field effect transistor, said modeling comprising determining conditions under which said channel region transitions from being in a partially depleted state to being in a fully depleted state, and said conditions comprising at least front gate bias voltage, back gate bias voltage, body resistance and body charge.