发明名称 Channel quality circuit in a sampled amplitude read channel
摘要 A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons. A defect detection filter detects particular defects in the media. In order to predict the bit error rate of the storage system, the channel quality circuit accumulates noise auto-correlation data, confidence metrics from a sequence detector, and cross-correlation of expected sample errors with actual sample errors.
申请公布号 US5987634(A) 申请公布日期 1999.11.16
申请号 US19970897339 申请日期 1997.07.21
申请人 CIRRUS LOGIC, INC. 发明人 BEHRENS, RICHARD T.;BLISS, WILLIAM G.;FOLAND, JR., WILLIAM R.
分类号 G11B20/10;(IPC1-7):G11C29/00 主分类号 G11B20/10
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