Decoder circuit for use in a non-volatile semiconductor memory device

摘要

A decoder circuit for use in a non-volatile semiconductor memory device including memory blocks comprises a decoder configured to select one of the memory blocks by decoding an address signal to produce a decoded address signal, a latch configured to latch the decoded address signal, and a switch configured to output a block select signal selected according to a mode of operation from the group consisting of the decoded address signal and a latch output, and further configured to block the latch output and select the decoded address signal when a suspend command is received, and to select the latch output and block the decoded address signal in response to a resume command that signals the resumption of the multi-block erase operation.