发明名称 |
Dram-Type Device With Low Variation Transistor Peripheral Circuits, and Related Methods |
摘要 |
A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region. |
申请公布号 |
US2016336056(A1) |
申请公布日期 |
2016.11.17 |
申请号 |
US201615218757 |
申请日期 |
2016.07.25 |
申请人 |
Mie Fujitsu Semiconduictor Limited |
发明人 |
Clark Lawrence T.;Shifren Lucian;Roy Richard S. |
分类号 |
G11C11/406;G11C11/4072;G11C11/4091 |
主分类号 |
G11C11/406 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
Kuwana JP |