发明名称 |
PLL circuit and image display device |
摘要 |
The present invention provides a PLL circuit that makes a voltage-controlled oscillator converge to a stable state within a short time and generates a clock signal with high stability even when discontinuity occurs in the period of a reference input signal. The PLL circuit of the present invention has a voltage-controlled oscillator for outputting a clock controlled, a first counter reset by the reference input signal having one period longer than a reference period within a predetermined period for outputting a first signal, a second counter for outputting a second signal, a reset pulse generating circuit for resetting the second counter, a loop filter for holding and outputting the control voltage varied by a phase error signal and a discontinuous input detecting part for detecting the reference input signal input initially after its period becomes longer than the reference period.
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申请公布号 |
US2005040872(A1) |
申请公布日期 |
2005.02.24 |
申请号 |
US20040915340 |
申请日期 |
2004.08.11 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
KINUGASA NORIHIDE;NIRASAWA YOSHIO;HAMAGUCHI HIDEO;OTA SACHI |
分类号 |
H04N5/06;H03L7/08;H03L7/14;H03L7/18;(IPC1-7):H03L7/06 |
主分类号 |
H04N5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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