发明名称 |
MULTI-PAGE CHECK HINTS FOR SELECTIVE CHECKING OF PROTECTED CONTAINER PAGE VERSUS REGULAR PAGE TYPE INDICATIONS FOR PAGES OF CONVERTIBLE MEMORY |
摘要 |
A processor of an aspect includes at least one translation lookaside buffer (TLB) and a memory management unit (MMU). Each TLB is to store translations of logical addresses to corresponding physical addresses. The MMU, in response to a miss in the at least one TLB for a translation of a first logical address to a corresponding physical address, is to check for a multi-page protected container page versus regular page (P/R) check hint. If the multi-page P/R check hint is found, then the MMU is to check a P/R indication. If the multi-page P/R check hint is not found, then the MMU does not check the P/R indication. Other processors, methods, and systems are also disclosed. |
申请公布号 |
US2016378684(A1) |
申请公布日期 |
2016.12.29 |
申请号 |
US201514751902 |
申请日期 |
2015.06.26 |
申请人 |
INTEL CORPORATION |
发明人 |
ZMUDZINSKI KRYSTOF C.;SHANBHOGUE VEDVYAS |
分类号 |
G06F12/10;G11C7/10 |
主分类号 |
G06F12/10 |
代理机构 |
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代理人 |
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主权项 |
1. A processor comprising:
at least one translation lookaside buffer (TLB), each TLB to store translations of logical addresses to corresponding physical addresses; and a memory management unit (MMU), the MMU, in response to a miss in the at least one TLB for a translation of a first logical address to a corresponding physical address, to:
check for a multi-page protected container page versus regular page (P/R) check hint;if the multi-page P/R check hint is found, then check a P/R indication; andif the multi-page P/R check hint is not found, then do not check the P/R indication. |
地址 |
Santa Clara CA US |