Selective FuSi gate formation in gate first CMOS technologies

摘要

The present disclosure provides a method of forming a semiconductor device structure with selectively fabricating semiconductor device structures having fully silicided (FuSi) gates and partially silicided gates. In aspects of the present disclosure, a semiconductor device structure with a first semiconductor device and a second semiconductor device is provided, wherein each of the first and second semiconductor devices includes a gate structure over an active region, each of the gate structures having a gate electrode material and a gate dielectric material. The gate electrode material of the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed during the silicidation process.

主权项

1. A method of forming a semiconductor device structure, comprising:
providing a first semiconductor device with a first gate structure over a first active region formed in a semiconductor substrate, said first gate structure comprising a first gate electrode material and a first gate dielectric material; providing a second semiconductor device with a second gate structure over a second active region formed in said semiconductor substrate, said second gate structure comprising a second gate electrode material and a second gate dielectric material; forming a pattern masking layer over said semiconductor structure that exposes said first semiconductor device and covers said second semiconductor device; with the pattern masking layer in position, performing a selective anisotropic etch process to said first semiconductor device to recess said first gate electrode material, thereby leaving a recessed first gate electrode material, and to form a cavity structure in said first active region, said cavity structure being in alignment with said first gate structure; with the pattern masking layer in position, performing a deposition process to deposit a strain-inducing material in said cavity structure; removing the pattern masking layer; forming a first silicide portion on and in contact with said first gate dielectric material by siliciding all of said recessed first gate electrode material; and forming a second silicide portion on and in contact with a portion of said second gate electrode material.