METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUIT

摘要

An integrated circuit (IC) having a memory for storing data also has a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory. A test interface provides test data. Flip-flops of the IC are connected together into at least one serial scan chain. The test interface unit receives test data including MBIST configuration data. The MBIST unit, in a first mode, tests the memory based on the MBIST configuration data at least partly in parallel with a scan test using the scan chain. Thus, both the memory and the logic circuitry can be tested in parallel.

主权项

1. An integrated circuit, comprising:
a memory for storing data; a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory; a test interface for communicating test data; and a plurality of flip-flops connected together into at least one serial scan chain; wherein the test interface unit is arranged to receive test data comprising MBIST configuration data, and wherein the MBIST unit is arranged, in a first mode, to perform a test of the memory based upon the MBIST configuration data at least partly in parallel with a scan test using the at least one scan chain.