| 摘要 |
The purpose of the present invention is to provide a flip-flop which achieves small area, low power consumption and high performance by minimizing cost added to sequential logic due to testability, and a system for driving the same. According to an embodiment of the present invention, a system-on-chip has a logic block which includes: a scan flip-flop for storing data using a passive keeper; and an on-chip clock controller which receives a reference clock for driving the logic block, generates an internal clock based on a high-level interval of the reference clock, and supplies the internal clock to the scan flip-flop. |
