发明名称 Method and apparatus for store durability and ordering in a persistent memory architecture
摘要 An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.
申请公布号 US9423959(B2) 申请公布日期 2016.08.23
申请号 US201313931875 申请日期 2013.06.29
申请人 Intel Corporation 发明人 Dulloor Subramanya R.;Kumar Sanjay;Sankaran Rajesh M.;Neiger Gilbert;Uhlig Richard A.;Chappell Robert S.;Nuzman Joseph;Cheng Kai;Kottapalli Sailesh;Liu Yen-Cheng;Kumar Mohan;Ramanujan Raj K.;Hinton Glenn J.
分类号 G06F12/00;G06F3/06;G06F13/16 主分类号 G06F12/00
代理机构 Nicholson De Vos Webster & Elliott, LLP 代理人 Nicholson De Vos Webster & Elliott, LLP
主权项 1. A method comprising: performing at least one store operation to cause one or more memory controllers to store data in at least one persistent memory device; sending a request message to the one or more memory controllers instructing the one or more memory controllers to confirm that the at least one store operation is successfully committed to a power-fail safe volatile buffer of the at least one persistent memory device without an error; sending a power fail control message to cause the power-fail safe volatile buffer to store the data in the at least one persistent memory device; sending a response message from the one or more memory controllers indicating that the at least one store operation is successfully committed to the power-fail safe volatile buffer of the at least one persistent memory device without the error; providing a residual energy budget for the power-fail safe volatile buffer that includes a retry of the store of the data in the at least one persistent memory device because of the error condition; and retrying the store of the data in the at least one persistent memory device because of the error condition without exceeding the residual energy budget.
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