发明名称 |
Method of Forming Layout Design |
摘要 |
A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch. |
申请公布号 |
US2016254190(A1) |
申请公布日期 |
2016.09.01 |
申请号 |
US201615150149 |
申请日期 |
2016.05.09 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Hsieh Tung-Heng;Lin Chung-Te;Wang Sheng-Hsiung;Zhuang Hui-Zhong;Chiang Min-Hsiung;Chiang Ting-Wei;Tien Li-Chun |
分类号 |
H01L21/8234;H01L21/304;H01L29/66 |
主分类号 |
H01L21/8234 |
代理机构 |
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代理人 |
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主权项 |
1. A method of manufacturing an integrated circuit (IC), the method comprising:
forming a plurality of gate structures, wherein at least one segment of the plurality of gate structures corresponds to a transistor to be subject to an electrical characteristic tuning process, the plurality of gate structures extending along a first direction and having a predetermined pitch measurable along a second direction, the predetermined pitch being smaller than a spatial resolution of a lithographic technology used to form the plurality of gate structures; depositing an insulating layer over the plurality of gate structures; and forming one or more openings in the insulating layer, the one or more openings having a width measurable along the second direction, the width of the respective openings being less than twice the predetermined pitch. |
地址 |
Hsin-Chu TW |