DELAY LOCKED LOOP

摘要

A programmable delay line comprises a delay stage responsive to an analog control signal and responsive to one or more digital control signals. The delay stage generates an output signal that is delayed relative to an input signal by a delay amount. The delay amount controlled by a value of the analog control signal and one or more values of the digital control signals. A method for controlling a delay locked loop circuit comprises providing, to a programmable delay line of the delay locked loop circuit, a one or more digital signals, and providing, to the programmable delay line, an analog signal. A first portion of a delay produced by the programmable delay line corresponds to values of the one or more digital signals. A second portion of the delay produced by the programmable delay line corresponds to a value of the analog signal.

主权项

1. A programmable delay line, comprising:
a delay stage responsive to an analog control signal and responsive to one or more digital control signals, the delay stage configured to generate an output signal that is delayed relative to an input signal by a delay amount, wherein the delay amount corresponds to a value of the analog control signal and to one or more values of the one or more digital control signals.